概要信息：

CADENCE SPB/OrCAD RELEASE 16.6 README -- 
Windows Version  
Installation Guide  
You can find the Cadence SPB/OrCAD 16.6 Release Installation Guide for Windows, Version 
16.6 (pcbInstall.pdf) in the Documents folder of the Disk 1 folder of the Cadence Product DVD.  
Migration Information  
Important migration information is contained in the Migration Guide for Allegro® Platform 
Products Release 16.6, which is available when you install this software or on Cadence Online 
Support (http://support.cadence.com). 
 
NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners 
are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx. 
System Requirements  
Information about minimum and recommended system requirements can be found in the 
Documents folder of the Disk 1 folder in the Allegro Platform System Requirements document 
(pcbsystemreqs.pdf) or on Cadence Online Support (http://support.cadence.com).  
 
NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners 
are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx. 
What’s New  
Product release notes are available at:  
http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi
ng/spb166/prodList.html 
KPNS  
The Known Problems and Solutions (KPNS) document is located at:  
http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi
ng/spb166/kpnsList.html 
Custom Environments 
Customers using custom batch files or scripts to set up their environments must add the following 
to their path. There is the potential that some Allegro products may not launch without this 
setting. 
%CDSROOT%\OpenAccess\bin\win32\opt 
 
Allegro® /SigXplorer® ABIML Libraries for Default Trace Models 
with Surface Roughness Effect  
 
The Allegro /SigXplorer ABIML Library includes ABIML libraries for SigXplorer default trace 
models with surface roughness effect. It is designed to provide accurate trace models in Allegro 
/SigXplorer without time consuming EMS2D solver runs. The Library is installed if you select to 
install Allegro /SigXplorer.  
 
Downloading and installing SPB Software 
Cadence software can be downloaded from: 
http://downloads.cadence.com 
 
Log in with a valid user ID and password and click the Windows tab. In the Windows tab, 
click the link SPB166.  
 
NOTE: OrCAD customers can contact Cadence Channel Partners to obtain their software. 
Cadence Channel Partners are listed at: 
http://www.cadence.com/Alliances/channel_partner/pages/default.aspx. 
 
Download CDs 1 through 5 and then extract the zip files into a temporary directory such as 
cdnstemp. This will leave you with a directory structure that is similar to:  
 
Disk1 folder 
Disk2 folder 
Disk3 folder 
Disk4 folder 
LibCD folder 
 
autorun.inf 
setup.exe 
setup.ini 
 
Complete the installation by running setup.exe from the temporary directory. You can 
install the following using the download: 
• License Manager 
• Cadence SPB/OrCAD Products 
• Allegro Design Entry HDL – AMS Library 
• Cadence SPB/OrCAD Client 
 
Consult the installation guide for detailed information.  
  
 
NOTE: If you are prompted to reboot, reboot the machine and log in with the administrator 
privileges login id to successfully complete the installation. 
List of Fixed CCRs  
• Enhancement CCRs 
• Bug CCRs 
Enhancement CCRs: 
 
CCR ID Description 
04027 shape check on micron data shows non-existent problem spots 
04113 aperture check error 
16223 Ratsnest requires option hanging etch and closest point 
22467 Plot pad holes 
23971 Plot drilled holes from Allegro 
31638 find by bus, diffpairs, xnets mg 
34060 Auto pin renumbering in symbol view 
43909 Redundant etch causes Propagation Delay DRC. 
54294 Request to create a fillet on Pin have arc c-line 
59644 Include Xnets in Find Filter 
75465 Add the capability run DRC within a user-defined area. 
105435 Allegro  Define Lists cmd doesn’t list diff pair set in CM 
126847 Generate NCRoute for plated and unplated 
139145 Enhancement to renumber pins automatically 
184728 Enhancement  to add  user defined angle in manual route 
189695 Import text file pin for allegro symbol creation 
195092 Fix property does not affect the usage of replace padstack 
202344 Xnets option in find filter 
202545 NCRoute to generate separate plated and non plated output 
212593 Add fillet for arc trace. 
212650 Ability to select different design units for display measure 
213447 Request closest endpoint to display rat from true endpoint 
215718 Diff Pair property missing in Show Element or Hilite 
217983 Allegro variant assembly drawing support of variant values 
226372 To add the skip option during assigning nets for Split Plane 
231461 Allow properties to Group dbids and axlCreateAttachment enh. 
231532 Request closest endpoint to display rat from cline endpoint 
233940 Define list by net property doesn’t allow wildcard search 
235122 Need some way to do query nets by diff pair property 
236511 Request to auto generate nctoolbits.txt file with NC Route 
239309 unable to  get the hanging etch to be closest endpoints 
246003 closest endpoint  not take in count 
258669 Design Partitioning does not allow Target change 
262130 Shape gap check needed 
262601 The function thieving support zcopy shape from etch subclass 
263692 copy and paste mode than one line in skill development form 
267881 Requesting redundant net report 
291066 add dc net pull down option to create split plane UI 
297523 Want to create separate file for plated/non-plated Slots 
299737 Need ncroutebits.txt file created automatically 
300203 Only Split Planes affected by antietch mods should update 
303636 Request Replace Padstack skip pins vias with fixed property 
329763 Enhancement  to add  user defined angle in manual route 
330916 Enhance Allegro to DRC by window 
339434 Split Planes affected by antietch mods doesn’t update dynamic 
340596 Theiving generation in Allegro 
343695 Design Partitioning does not allow Target change 
349024 Allow extraction of differential parts in PX3710 
350174 Allow extraction of differential topologies in Allegro PCB 
351407 be able to identify copper polygon metal hole 
354299 Option to create one thieving outline for all layers of brd 
356000 Requesting redundant net report 
358185 Allegro variant assembly drawing support of variant values 
359350 Replace padstacks by specifying a range of pin numbers 
362726 Enhance Allegro to DRC loop type routing. 
364074 Treat dimension text and leader line as single data base object in Allegro 
365955 Dynamic shapes should follow fill mode for edited antietch 
373774 Request to auto generate nctoolbits.txt file with NC Route 
374555 Requesting redundant net report 
382345 Plot drilled holes from Allegro 
383768 Enhancement  to add  user defined angle in manual route 
385337 ability to change existing Line Font 
386414 Enhance the Split Plane tool: Be able to "Slide" the Anti Etch line so as not to have to 
recreate the shape 
395294 ability to change existing Line Font 
395527 Generate NCRoute for plated and unplated 
398406 A function to change line font of existed line. 
399194 Requesting redundant net or loop report 
400741 capability to highlight a group build by thieving 
400870 Ratsnest requires option hanging etch and closest point 
406594 thieving from route keeping 
408187 Enhancement  to add  user defined angle in manual route 
418498 Enhancement  to add  user defined angle in manual route 
419886 Add 10 degree routing function for new intel chipset routing requirement 
426822 Zig-Zag Routing function requirement 
429023 To add the skip option during assigning nets for Split Plane 
430641 Enhancement to cancel all at once for Select Net while in Create Spit Plane 
431423 Add 10 degree routing function 
432200 Fillets with an arc are required for Flexi designs 
432273 Enhancement  to add  user defined angle in manual route 
436033 Requesting redundant net report and DRC for looped Clines 
441718 Ratsnests cannot keep in Closest endpoint. 
442583 Need method to report and remove redundant etch 
453139 Generate NCRoute for plated and unplated holes separately 
453356 Would like Pin Renumber utility enhancement for multiple row/column support 
454431 option to retain last routed trace width 
464447 Ratsnest requires option hanging etch and closest point 
470641 Request to auto generate nctoolbits.txt file with NC Route 
477918 Enhancement to add  user defined angle in manual route 
479892 We need to be able to route with any angle. Example 10 degree 
494962 Design Partitioning does not allow Target change 
495801 Request closest endpoint to display rat from cline endpoint 
497906 Change Matched Group targets while in partitioned design 
498396 Requesting a "True Closest Point" in Ratnest Display....duplicate to master CCR 16223 
500831 Separate files for plated/nonplated holes on NC route. 
509961 Print drill holes inside through hole pad 
510555 Values in Variant assembly drawing 
517750 Ratsnest requires option hanging etch and closest point 
520543 Would like to be able to create Gerbers of drilled holes 
522041 Enhancement  to add  user defined Line Lock angle in manual route 
524637 expand subclass name length limit (variants impact) 
528632 Enhancement for a way to force an  Update to all Dynamic Shapes 
533207 Enhancement to add user defined Line Lock angle in manual route. 
535431 ability to plot pads with holes 
537295 Display > Measure to be enhanced to show multiple units 
538059 Shape is out of date but status says it's not out of date 
552240 Windows login with period(.) crashes symbol editor 
556709 Auto generate nctoolbits.txt file based off parameter file 
558114 Display drill holes in artwork 
563504 Update Symbols is changing text justification. 
569634 Plot drilled holes from Allegro 
576107 Automatically renumbering pins in Allegro Package 
576496 Value for variant assembly drawing should be taken from value in Variant.lst, and not 
from Component Value subclass 
577117 ratsnet are visualized from pin after partial routing also 
582532 Would like the fixed property for a net to apply to every element on the net including 
padstacks 
587479 need ability to plot solid pads with holes from the drills 
594244 Duplicate of CCR 22467 - Request to plot holes in padstacks 
600475 Enhancement  to add  user defined angle in manual route 
605831 Allow single instance symbol refresh 
614364 ability to change existing Line Font 
615234 Enhance Allegro with user definable line locks. 
615401 to be able to plot pads with centers 
615749 Plot drilled holes from Allegro 
616376 redundant net or trace loop report 
618890 Plotting with holes in Allegro. 
619129 Ability to paste multiple lines in skill console 
619405 Variant Assembly Drawing should use Value for specific variant and not the Original 
value 
619690 ENH- Would like to have Variant names longer than 15 Character 
619966 option to display "units" with the dimension values 
621131 Change line fonts in Allegro 
625639 Same export units than the design units. 
625881 a check to determine for redundant or looped routing 
632744 Allow Allegro to create a slot display without executing nclegend 
633809 Updating symbols is changing text orientation. 
636431 Plot drilled holes from Allegro 
638673 DRC by object or window 
639286 Create Variant Assembly Drawing with alternate Value/Part number. 
642595 Request to auto generate nctoolbits.txt file with NC Route 
642794 Enhancement request for Adding Snap to in RMB menu for Edit > Vertex 
656544 Option to create one thieving outline for all layers of brd 
658019 Enhancement  to add  user defined angle in manual route 
661490 Overlapping static shapes cause Artwork to abort. 
662370 No artworks is generated for overlapping shapes with same net name 
662877 Request to be able to use last line width while routing 
665003 Enhancement to add  user defined angle in manual route 
667149 Wrong value used in Variant assembly in PCB Editor 
674612 Enhancement to Replace Padstack in general edit mode 
682349 Overlapping Shapes do not allow Gerber generation 
683441 Place replication should apply text locations from seed group to replicated groups 
696666 Need more enhancements in Align component feature, similar to PADS. 
702337 Overlapping Shapes do not allow Gerber generation 
703785 ability to have user defined angle in manual route 
707891 Silk text fix when updating symbol 
713279 Enhance Allegro to export in IPC-2581 format 
721794 Request closest endpoint to display rat from true closest endpoint 
723851 Request to auto generate nctoolbits.txt file with NC Route command 
724846 Performance : Highlighting from Net class in 16.2 is slower that highlighting by 
Net_Physical_Property in 15.7 
729112 Allow single instance symbol refresh 
730694 Shape shorts other nets and gives DRC but reported as Up to Date. 
731805 Enhance request : support "fillets" by module 
733559 Need ability to re-number pins in allegro symbol editor 
735527 Enhancement: Introduce Database diary option in Allegro 
737352 create variant BOMs with alternate PCB footprints 
737393 Fillets lost during create module 
737647 Enhancement request for Adding Snap to in RMB menu for Edit > Vertex 
740162 Enhance Allegro PCB Editor use model when adding NULL net copper 
743905 User can modify constraints in a partition and update to master board. 
750664 Request for the Subclass character length limit be expanded to more than 19. 
751494 customer would like to have Variant names longer than 15 Character 
758863 Generate NCRoute for plated and unplated 
768626 Suggest to add a new option [Last edit point] in Ratsnest points 
768634 Display netname in pin location required. 
777054 Rename automatically a group of pin number 
778682 Requesting forced auto update of dynamic shapes regardless of out of date status 
783926 The "create module" command should include the fillet shapes. 
786582 Allegro Check Window Area command 
790052 Allow single instance symbol refresh 
790183 Enhancement: Introduce Database diary option in Allegro 
790559 ability to have open drill holes in artwork 
794546 Generate NCRoute for plated and unplated 
808198 Process for assigning a Constraint Region name to many shapes at the same time. 
808545 Requesting the ability to change the radius of Circle in shape>circular & add> Circle 
and arc 
814571 Enhance Ratsnest points to include a rat from routed endpoints setting. 
815400 Ability to edit circular shapes 
819615 SKIL Command to unlock Csets or Purge locked Csets 
820409 A skip option during assigning nets for Split Plane 
824598 Update DRC by area function requirement. 
827720 Updating testpoint information when replacing Padstack 
828736 Include Unit name with the value in Dimension text for Dimension > Linear 
830225 Introduce Database diary option in Allegro 
831965 Request to change the radius of arcs 
834586 Allegro ratsnest needs to go to nearest net object 
837708 Enhancement request for Adding Snap to in RMB menu for Edit > Vertex 
839843 Request - rband_angle_offset also work with the slide command. 
840306 expand subclass name length limit (variants impact) 
841704 Request - GUI to work with the  rband_angle_offset variable 
842070 Ability to route segments with user defined angles. 
844670 Ability to route segments with user defined angles. 
851929 Generate rou file for plated and non plated slots 
854359 Ability to add/change, radius/diameter of circle with add>circle & Shape>Circle 
854373 The customer wants to control the same net "Shape to Shape" Gap in one Shape 
boundary. 
856005 Update DRC by portion of bus function request. 
857016 Documentation for axlMatchGroupCreate is unclear. 
857288 show measure and axlAirGap fail to measure mask classes if no common layer exists 
861186 Fillets lost during create module 
862506 Display Ratsnest points option 
864596 Request to have "auto tool select" button for ncroute similar to NC Drill 
866285 Need ability to move lines and text to different classe 
867851 Document need to be improved for axlGetVariableList function. 
868789 To add the skip option during assigning nets for Split Plane 
872378 Design Partitioning require ability to change constraints in a controlled way by Partition 
Designer 
874440 Add connect can display Normalize angle of Cline to easy identify the trace angle for 
any angle rout 
874499 Line Lock can let users input angle they want. 
874508 Rband_angle_offset can automatically change 10 to -10 by sense the direction where 
User put the curs 
874584 Add offset (rband_angle_offset value) to Options panel 
875809 Enhancement for allowing VIA_AT_SMD_THRU property on Symbol Drawing file 
879339 Enhancement to renumber pins automatically 
880969 "Enable HTML" should be ON by default 
881840 Allow overlapping of shapes 
884677 Enhancement to allow thieving on all layers at the same time 
884918 Enhancement to add thieving areas by rectangular selection 
884926 Include layer name in thieving name. 
886187 Photoplot log file should show an error message if 'Undefined Line Width' is set to zero 
886333 Enhance align component to enforce constraints 
888061 Enhancement to renumber pins automatically 
888406 Need a function to detect and report loops or redundant clines in the design. 
889460 Request - variable to set the default folder/directory for the export libraries command 
895551 Request change to how fillets are voided when shape via clearance is set to Termal/anti 
896021 Request ability to filter the panel outline 
897223 Ratsnest does not show nearest connection point 
899562 support for SPB16.5 on SUSE 11 operating system 
899592 Vectorize text width value should adjust with the User Units change 
899904 Text location of module doesn't follow to other text locations of module replicated by 
PlacementEdit 
900479 Import logic reports incorrect warning. Symbol not found when the issue is sym doesn't 
fit drawing 
900961 Need details regarding ERROR (SPMHDB-243): Cannot modify object. FIXED 
property found. 
901726 algroskill.pdf needs clarification for DRC attribute 
903980 Need option to highlight nets by Net_Physical_Type or Net_Spacing_type 
906896 Ability to plot drill (center dot) of a TH pad. 
906902 Manual Void will be lost without any warning through the context RMB menu at Shape 
Type changing. 
908725 about the difference of contents of Techfile between Layout menu and CM menu 
914598 Enhancement request for providing Snap to option in the RMB for Edit > Vertex 
916125 Request variables that will set the database units and accuracy. 
916231 Request - Place replication should apply text locations from seed group to replicated 
groups 
917205 Enhance the Embedded Layer Setup for Top and Bottom layers Body up and Body 
down. 
917501 Preserve the Text Location in the seed circuit and place the text in the replicate block at 
the same location 
918472 Save Text location in Seed Circuit and place text at the same location in Replicated 
circuit 
920340 Request - smoother handling of file association for non-admin user with UAC turn on. 
923608 Edit Vertex command needs RMB "Snap pick to" options 
926731 Highlight of nets associated with components. 
928699 "WARNING(SPMHA1-299): Create symbol multiple text lines are not supported on a 
xxxx" needs to be refined 
929061 Ignore the Illegal Warnings in Photoplot log for pads/vias for "unused pads 
suppression" when generating artwork 
929794 Add Snap Pick to option to Edit>Vertex 
934997 Lck file creation is unnecessary if board opened using Allegro Free Viewer 
936830 Request to have delete function for Pins in pre-selection popup in Package Editor 
937392 SKILL function to change line segment layer. 
940038 Enh - Request to exhibit Display >  Measure readings in both metric (mm) and  Imperial 
(mils) units 
943800 Change in the Header information for Cross Section Report 
943955 Request the ability to remove unused Pins from BGA using Indirect Attach 
944836 RMB command Snap Pick To in Edit Vertex. 
944847 Another instance of Aero in conflict with opengl display issue regarding temporary 
highlight- Win 7 
945394 Add batchhelp for ncroute 
945429 Generate NCRoute for plated and unplated 
946313 Skill should provide equivalent of "write" command 
951081 enhance display measure to output other units in addition to the DB units 
954083 place replicate should retain text locations of seed circuit 
954363 Request closest endpoint to display rat from true closest endpoint 
954392 Convert Cline Corners to Arcs 
954508 Request Improve Import logic  Warning Message when symbol extents are greater than 
the drawing 
954698 Add Block definitions in DXF interfaces 
955564 set "hole to" parameters in spacing constraints mode default 
955723 Align x-coordinate text to Right in placement file (Export > Placement) 
956940 Enhanced Arc Sliding 
956993 Photoplot log file error message for 'Undefined Line Width' 
959360 about display ratsnest 
960233 Origin of move command for stacked via should be origin of via. 
963247 Request to open Navigation window for document browser, along with HELP from 
Allegro. 
963431 Add Squircle (circle in a square) as a balloon type in dimensioning 
965031 Enh- Append the db diary feature of APD in Allegro too 
966842 place replicate should retain text locations of seed circuit 
967324 Display netname in pin location required 
968333 Request closest endpoint to display rat from true closest endpoint 
968573 ENH:Remove non conductor subclass 
969274 Add ability to create different balloon types in dimensioning 
969804 Need to remove User Defined mask subclass when the mask is deleted from padstack 
969984 Ability to import pin locations from a text file into symbol editor 
973925 Ability to suppress specific net single pin - no pin 
975675 Zoom to object in Allegro should work for all Application Modes when selecting the 
same object from Design Entry CIS 
976679 Request to create placement file with board name 
976701 Request to use database user unit when no unit is found in art_param.txt file when 
generating artwork 
977983 Enhancement: create artwork with shapes overlapped. 
979181 Plot drilled holes in artwork 
979799 Ability to edit constraints on a partitioned block 
980818 Ability to connect embedded component using two microvias per pad 
985934 Add update symbol to RMB in placement app mode 
985949 Arc not available with RMB command when editing a shape boundary 
987604 Request - Application to prompt the user to rename when period is found in the package 
symbol name 
988088 Edit > Move of Vias with incremental coordinates entered at the command line makes 
no sense in 16.5 
988573 Enhancement: Hide of rats cluttering up the screen or de-clutter 
989057 Enhancement: Documentation needs correcting algrostart.pdf page No. 57 
989636 Allow leader line dimensions to have optional text as part of the dimension 
990755 Ability to retain options selected in RMB Customize menu 
991115 Preserve text locations of the seed circuit for place replicate apply 
991537 Output number of holes from Probe drill log file to command window 
992730 Enhancement to renumber pins automatically 
992737 Resize the list of existing nets window in the options panel in logic net logic mode 
mentor competition 
994173 Unable to use axlDBCreatePropDictEntry SKILL function to create a user defined 
property for a netclass. 
995172 Ability to drag and drop board file into dbdoctor_ui dialog box 
996527 Modification in the Document for the Skill command axlDBAssignNet 
998339 Remove dependency of Define BBvia / Microvia from Design stackup. 
999767 Enhance Allegro's pastemask to pastemask checking 
1000351 Min_line_width should not change thermal ties width 
1000815 DEVICE_TYPE has comma, a part name generated with PPT merging in Packager XL, 
causes problem with BOM in CSV format. 
1003692 Request for a variable in the env to use customized parameters 
1005635 dbdoctor did not create backup during uprev. 
1005903 Enh: Retain last file name for NC Route 
1007129 Request to update standalone Allegro Free Viewer 
1009637 Maintain Ref Des location when replicating modules 
1009736 Import logic causes cline width changes on xhatch shape 
1010196 Q:Why directories path are not following CDS_SITE settings though some commands 
are under “read-only 
1011015 Modify earlier release warning popup to include version ID of older/newer design 
1011858 feedback on "Slide New" feature 
1016463 Define generic layer stack up for Microvia, which can be used on board with different 
stack up 
1016759 Retain last file name for NC Route 
1017237 Warning message during netlisting is not helpful in cases where input board file has 
smaller outline 
1019477 Modify snap-to-segment so that it recognizes a rectangle edge as a segment 
1023839 Create Artwork gives Error-Shape at (X Y) contains void at (X Y) which touches 
another shape, has incorrect coordinates 
1024694 Add ability to create different balloon types with Associative dimensions 
1025328 Change the default format for NC Drill parameters to 2.5 to make it consistent with 
Artwork format. 
1028734 Enhancement for uprevving package file saved with pre 16.X version saved as brd file 
1031059 Tool should not "Create missing layers" with the same name if duplicate layers exists. 
1031177 artwork long name size 
1031829 Enhancement request to support overlapping partitions. 
1031962 dbstat -t returns Librarian EOL when file is saved with an ORCAD license. 
1034761 Enhance "Snap pick to" menu. Need to have a body center option. 
1036416 ENH: Functionality to update 1 instance of symbol? 
1037546 Enhancement for Fixed property on cline and symbol/ component 
1042746 Request - Changing the wording  of IDF warning message when more than one place 
bound outline exist 
1044230 Fillets are causing spacing clearance larger than the defined value in CM 
1050351 Need different display name or icon for Viewer Plus (Free) with right mouse button 
click – Open With 
1052032 BUG : Cross-section report in mil even pcb is in mm 
34734 Customer wants function parallel copy 
131534 net and ball names on die pad, bump pad, wedges and ballpad 
131547 Distance/Angle Key-in for move slide copy 
155271 Polygon, fence, and window selection. 
183253 drill output and legend to start numbering at top of package substrate, not including 
diestack layers 
228228 Display pins no. and pin net name directly after place comp. 
245817 Thieving - request for other element types besides vias 
259349 Enhancement for Display Measure to retain subclass setting 
303196 Constraint for the drill hole vs. soldermask 
318254 Stream out option to flatten structures rotated at any angle 
339147 Request to add multiple Die Flags at the same time 
339447 3D Viewer take too long time to open real design 
367779 Enhancement for Display Measure to retain subclass setting 
368098 Wants a line added to thieving style. 
371570 Approximation of arcs when using Output all clines as boundaries in stream out 
375971 Approximation of arcs in GDSII 
400846 display net and ball names on die pad, bump pad, wedges and ballpad 
419614 Check between Smask and via drill 
421496 APD should exclude WB layer, as a drilled physical layer` 
460825 Enhancement request for thieving command. 
497149 Getting APD to accept the routes composed of multiple polygons 
516898 Enhancement to automatically change subclass in the Options tab. 
555625 Problems reading GDSII files with import stream 
574133 Requesting a "Diagonal" Pin Pitch be added to BGA Generator - Pin Arrangement form. 
583707 request to have the bond wire profiles listed as a class/subclass 
595559 NCLegend and Manufacturing subclasses are not in sync when WB layers exist 
630001 Color files do not save bondwire profile visibility. 
647635 SiP Layout - Visibility views are not displaying wirebonds that are included in the film 
659652 Wire layer visibility cannot save in color view file. 
765637 net name display with display-pin-text does not dynamically change with the swapped 
pins 
818113 Request to support Lead Frame design in the Cadence Packaging tools 
822973 Enhance the DXF output to be able to retain the Colors assigned in the SiP tool for each 
layer. 
860712 Artwork can not generate by ERROR: Shape at (xy) contains void at (xy) which touches 
another shape 
863929 allow for diagonal spacing and angle for interstitial BGA creation 
888290 Die Generation Improvement 
907825 Heal command dose not works correctly. 
914460 How to purge unused module from Update Symbol function? 
914532 APD 3D Viewer license was used even this feature was turned off in APD by user 
916210 profiles are not stored in color views 
933675 How to remove the via_structure. 
934600 Enhance the Export Board Level Component to output all needed files for use in HDL. 
938691 DXF_OUT should export color information 
957908 export board level component pin delay should have a net browser to only export some 
nets 
1010897 3D Viewer license cannot release after close 3D Viewer. 
1021102 Do we have any skill function to retrieve the position of an open form window? 
1029247 Ability to add wirebonds to a die at the library level. 
1038612 Carriage Return in Package Design Integrity Check report breaks the link for XY 
coordinates. 
1041128 Enh - Via Pin Alignment in Tools - Package design integrity check for APD 
12577 Resetting part references to ? resets the package design 
20701 Annotation only change designator, treat reference as hard 
21609 Ability of moving pin number and name when generating part 
33956 Ability to set gate id, annotate, keep gate assign, set refs 
74510 Ability to turn off specific DRC markers. 
111399 TCL: option of invisible net alias 
124214 move pinname and number separately while editing in library 
124736 Enhancement in DRC report 
153574 option of display enable/disable for Net Alias 
163978 DRC exception table or ignore option at pin level 
176359 ABLE TO IGNORE DRC ON SELECTED NETS/PINS 
258906 make net alias invisible in Capture 
270946 Wanted to lock some Part Reference values during annotation 
324245 Pin name/number movement in the library >> Part Editor 
338235 TCL: Automatic synchronization for externally referenced designs 
339378 Automatic synchronization for externally referenced designs 
361079 Cannot see lengthy paths in "Select Directory" while File >> New >> Project 
381801 Method to lock "Designator" 
384949 Allow pin text (name) movement in the library editor 
385581 Option to lock refdes 
396374 Hard_Location for part references 
464628 Wants to be able to move and rotate pin numbers in the library editor 
480002 Global replace for Off page connector 
533895 TCL: DRC A method to check the Reference Designator Prefix 
545360 Global Replace command not working for a bus 
556262 Location browse window in File, New is to small 
570012 Global replace for Off page connectors and Power/Gnd 
582838 Rotate individual pin number in part editor 
585841 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
586798 Capture invokes slow when CDS_LIC_FILE points to a WAN server 
613386 Invoking Capture is slow 
620319 Automatic synchronization for externally referenced designs 
621054 Renamed net in netlist isolates components from the rest of the net. 
628823 Enhancement to enlarge select directory window size horizontally. 
632624 Select directory window for new project should be re-sizable. 
645834 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
650011 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
650130 TCL:Option to disable power nets from cross probing 
652202 Update the Select Directory window to current Windows look and feel 
656562 Enhancement : Capture.ini path should be user's home location 
682645 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
691018 Option to lock refdes 
691502 Option to lock refdes 
692025 TCL:close all the schematic pages 
693632 Property similar to hard location which when put on a part will be skipped while 
annotation even with Unconditional refer 
694609 Property similar to hard location which when put on a part will be skipped while 
annotation even with unconditional refer 
702468 Enhancement for advanced search parts with specific property values. 
713626 TCL:Closing Multiple Schematic Pages at once 
726621 TCL:Command to close all open tabs of a design except “Project Manager”. 
733955 Missing pin swap information when back annotating from Allegro 
736980 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
740538 Enhancement: TCL:Option to close all opened schematic pages only in Capture. 
743894 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
750501 Method to lock "Designator" 
750894 Improve documentation for 3D viewer 
751388 TCL: Function to close all open tabs of a design except "Project Manager.” 
752446 Select Directory window is very narrow. Directory selection is difficult for long 
directory names. 
756925 Capture update file or directory browser to new Windows style 
776027 Enhancement: Ability to re-size the “Select directory” for netlist window. 
788944 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
791392 TCL:DRC check where two terminals of any discrete part tied to same POWER/GND 
net 
795861 Add PARTGROUP to Annotation and to the Heterogeneous part itself 
797862 Ability to open 16.2 design (only to view) in v16.3 without converting it 
797898 TCL:Option to retain schematic level property while linkdatabase part. 
800346 Way to auto increment refdes across schematic folders within design 
821994 Move Pin Text when creating a new symbol 
822281 Device/Net/Pin Name character limit increase option needs to be documented 
834091 ENH: Ability to move pin name and pin numbers at library level 
845314 Ability to ignore parts during annotation 
846373 TCL:Date format under Design Properties 
848582 TCL: Command to close all open tabs of a design except "Project Manager" 
850844 exclude a selection within a page from annotation 
851830 Ability to disable cross-probing for specific net in one direction (Allegro to Capture). 
854472 Select Directory window is very narrow. Directory selection is difficult for long 
directory names 
866699 Ability to crossprobe with filter like parts / nets 
866784 ENH: Ability to move pin name at library level 
872379 TCL:Closing schematic windows or tabs all in one 
872968 Enhancement: TCL: Option to display flat net names against all the nets 
873550 ENH: TCL:Function to sort parts by library name in Design Cache 
882575 Option to disable cross probing for power/ground nets. 
884192 Enhancement: TCL: DRC for H-pin and H-Port mismatch 
887202 ENH:TCL:Intersheet reference for H-ports should be like as of offpage connectors 
889816 Cross probing of power nets from Allegro causes Capture to hang 
890720 ENH: TCL Script to place the entire Orcad library  in one DSN file at once 
894726 TCL:ISO 8601 for naming archive 
895496 Enhancement: Capture should remember the docked position for a project 
896817 New TCL/TK commands help for attached file containing CIS TCL interfaces 
898029 ENH: TCL:To show net alias clearly in print out if alias has underscore 
905538 User should be able to change the bundle block 
907977 ENH: Cadence Product Choices dialogue box is not wide enough to display entire name 
of products 
908810 ENH: Web resources link are not pointing to correct pages 
908893 TCL:Waiving DRC's in Capture as being done in PCB Editor 
914262 ENH: Disable CIS warning Cannot place database part 
916455 ENH: Preserve CAPTURE.INI settings from one version to new version 
921919 ENH: The H block reference must be picked from occurrence value 
925830 Option to lock refdes 
927594 Describe ERROR[CAP0095] in Capture Messages Reference Guide 
931719 Option to lock refdes 
937599 ENH: What are the manual and automatic properties in Title Blocks? 
942514 Docking state of Project manager window is not remembered when a project is closed 
and reopened 
944045 User would like to be able to replace cache on several parts at once 
952741 ENH: Uprev process should save the existing 16.2 design on open 
958214 ENH: Make Select Directory window wide such that even long paths are visible 
967425 Enhancement: Option to move the pin names/numbers when creating new part or open 
part from library. 
968679 ENH: Option to close all open schematic pages. 
969564 Waive DRC option in Capture, as is available in PCB Editor 
970133 ENH: Properties displayed in datatip should be customizable 
975613 Enhancement: Option to move the pinnumber and the pin name in symbol in library part 
975684 ENH: Reviewing lower version design on higher version should not change the database 
format 
977238 ENH: Last column in browse spreadsheet can't be increased in width till other columns 
are narrowed 
979770 Update netgroup box at change 
982720 ENH: Option to preserve section of homogeneous package in annotation. 
985385 ENH: Data-tip of pins should be more informative 
988097 ENH: Add Off page connector in Global Replace dialogue box. 
997521 Back annotation doesn’t work if user renames refdes as per grid based 
998469 Add 'NET_SHORT=YES' as default in allegro.cfg 
999421 Enclosed Polyline goes black and white when moved 
1000419 Net properties to be displayed on tooltip 
1005805 Project Manager not docked as set 
1010988 ENH: ADD ISO 8601 Date Time format to Capture 
1011871 ENH: The H block reference must be picked from occurrence value 
1012008 Enh: Option to remove symbols (! and ^) from Irefs. 
1014750 Bus shown as bundle in netgroup 
1019868 Warning(ORCAP-1589) Net has two or more aliases 
1023433 ENH: Finer mouse zooming 
1033822 ENH: Function to  only annotate newly added parts in bottom design of hierarchy 
1041492 Enh: Pin names of pins placed on right boundary of part must start from same X 
location 
1042710 ENH: Add a note mentioning the limitation of Autowire > Connect to BUS in capture 
user guide 
754719 Bathtub Curve of voltage domain. 
860776 option to ignore the ibis-ami model clock ticks 
15280 Multi valued cells from other columns in CIS 
70237 leading zeros in CIS Part Manager deleted 
151466 Need a option to define more than one PSpice model in CIS 
214027 Multiple values of Implementation be supported in CIS Explorer 
214262 Permit specifying multiple datasheets in place DB part 
334450 Ability to have drop down for other columns in CIS. 
370024 Multi valued cells from other columns in CIS(datasheets too) 
417511 Multi valued cells from other columns in CIS(datasheets too) 
657611 Enhancement : Ability to add alternate PSpice Models in CIS database 
755660 alternate PSpice Models in CIS database 
768643 TCL:DSN file auto-merge function. 
800927 OrCAD CIS should support same character limit of VARCHAR data type as of 
MS_SQL 
835721 TCL: library cache needs to updated across the network 
855425 ENH: Ability to "link database part" for externally referenced designs 
866168 ENH:Capture must execute the CIS query without editing any of the fields 
869395 Enhancement: Allow CIS related operations for schematic inside library 
871136 Ability to change 3D footprint view unit 
878340 TCL:Library location while saving the ICA part 
884935 Database column names enclosed in double quotes 
889378 Enhancement: Option to get drop down list for Datasheet in CIS explorer. 
892098 Part Manager->Update Selected Parts Status should query only one time to database for 
unique parts 
896659 Help about "Orcad Capture CIS" shows UNLICENSED 
917498 Ability to select the custom query once user has re-invoked CIS. 
923271 CIS BOM report should export part number for "Do Not Stuff" part also. 
930981 ENH: CIS must remember the library in which ICA part are saved and point to same 
library next time 
956370 Enh: Ability to have multiple datasheets associated with same part in database. 
959466 ENH: More than one DataSheet availability on DS Field 
959861 Enhancement: “Link Database part” message enhance request 
985826 ENH: Feature to link part of an externally referenced design from part manager 
987539 ENH: Export Part Number of not stuffed parts to CIS BOM 
988037 ENH: Flexibility to change unit of measurement in footprint viewer 
1004543 Need new functions for Capture CIS 
1033689 ENH: Feature to link part of an externally referenced design from Part Manager 
721776 Ability to view objects (nets, xnets, diff pairs) based on the top level name in flat 
structure 
746645 Genview should ask for confirmation if existing schematic page is overwritten 
791439 Ability to view objects (nets xnets diff pairs) based on the top level name in sub design 
structure 
883030 Enhancement: Displaying project name in the status bar of Project Manager window. 
893922 Ability to sort the filtered result in Part Manager 
894225 Ability to scroll (vertically or horizontally) in Part Manager window with the scroll 
mouse. 
898181 Display full path in window title bar 
898922 Improve help system for BOMHDL 
908548 Enhancement to DE HDL General options list 
913485 “Zoom by points” under Global Navigation window is little confusing. 
917896 Enhancement: error-finding capability with Save All 
944378 Genview should verify the destination view 
989585 Additional information to add page name property while following TOC flow. 
1030734 Making a net group and dropping the net group object on the wires should not place the 
net group name on top of wires 
1034821 'Go To Page/Symbol' navigates to incorrect schematic page 
1041833 “Creating zones on Page boarder” topic in concepthdl doc should have a link to 
concepthdl_ut_ug.pdf 
33700 Re-assign the name of Xnet 
559654 Display Element slow performance with RPD spreadsheet displayed. 
636639 Changing the referenced CSets takes too long to complete 
710123 Bundles in Ratsnest Bundle Properties Sort by Net Name 
742409 Add ability to import generic spacingphysical CSets 
858611 Add ability to import generic spacingphysical CSets 
859287 User would like to be able to filter out single pin nets from the CM display 
861974 Frequency set on Net needs to be used by Xnet during simulation 
869414 CM Audit requires a function to validate report and remove invalid or empty Diffpairs 
874204 Request to Add the ability to import generic Spacing and Physical Csets 
883167 Setting the object filter should not expand all rows. 
883275 Misleading message when creating Electrical net class that exists in other domain. 
900439 Enhancement to have a better editing for spacing parameters while creating new SCSet 
and Same Net SCSet. 
903733 cmgr leaks GDI objects 
918511 Ability to import/export generic physical and spacing constraints 
961864 Enh: Ability to extract a net (sigxp) from a replay script 
964951 Requesting consistency when editing multiple cells in constraint manager. 
981123 Add analyze to the OrCAD PCB Professional Constraint Manger Menu to make it 
consistent with other Allegro Tiers. 
983466 Enhancement request for Membership dialog of Match Group and Class 
1000825 Net Sorting for CM Pin Pair should sort by net name. 
1024385 small restore from definition selection window 
841657 All ports of virtual interfaces are inout in schematic regardless of VI definitions. 
882366 ENH:Provision to deselect banks from getting connected to an interface and hence 
selecting all other 
1008112 port directions set inside FSP need to be used for ports in schgen 
1011487 Ability to insert text directly in “Edit Group > Group Description” field 
803628 Allow PSpice libraries to be installed in Silent mode 
903158 While installing need a comment "select same working directory to retain 
customization". 
931448 Give a Warning pop up if user do not provide the License Server Path during Product 
Installation 
955800 Ability to install PSPICE Libraries in Silent Mode. 
1021155 Allow space in the path where the ini and exe file for Silent Install are stored 
900116 Metadata API should update the already loaded metadata. 
968832 PDV changes the "-15v" global pin name changes to "_15v" 
980837 The Instantiation_Packaging_Validation_Type=1 should be the default setting 
1009685 csv2ptf - no ptf file generated and also does not give any warning or error message to 
debug 
912421 PI Network Analysis fails on this routed power net 
1029681 rename the MORE button in PDN analysis form to something more descriptive 
08512 Enhance Analog Data tips to display the bias information 
10678 Have the ability to reduce the resolution of data read into 
21212 DELTA parameter other than RELTOL for .WC analysis 
22475 spice concepthdl : visibility on each operating node 
25207 Enhancement request: Support for IBIS in PSpice 
25822 Bias point (voltage and current) display in ConceptHDL 
37733 IBIS to SPICE updated translator in Model Editor. 
177776 AA controller should allow expressions for components 
207274 TCL: Allow support of tolerances for Global parameters 
287773 Add an IBIS 3.2 primitive to PSpice 
329167 model import wizard should detect parts with invisible pins 
333591 IBIS to SPICE updated translator in Model Editor. 
335252 IBIS to SPICE updated translator in Model Editor. 
363056 Allow support of tolerances for Global parameters 
416436 How to pass parameter value in sensitivity analysis? 
475030 Need new IBIS to PSpice translation method 
511843 Request for support for IBIS in PSpice 
518221 Need a utility that will translate IBIS models (3.2 and beyond) into a PSpice format 
567494 IBIS v3.2 model support in PSpice 
570133 PSpice support on multi-core processor 
579177 Option to import/support IBIS version 3.2 models 
610775 IBIS to PSpice translator for version 3.1IBIS model 
617774 IBIS v3.2 model support in PSpice 
619446 Translation of  IBIS version 3.2 models to PSpice 
623746 Enhancement in model import wizard - display pin name in symbol graphics 
624867 Include the expression value in Sensitivity analysis 
635267 IBIS v3.2 model support in PSpice 
638941 IBIS v3.2 model support in PSpice 
639341 Need new IBIS to PSpice translation method 
641604 Need new IBIS to PSpice translation method 
659571 TCL: Option to support TKNEE with Derate Factor, enhancement 
710467 PSpice support on multicore processor 
733346 Translate IBIS 3.2 models 
753683 TCL: Enhancement: Provide Property to ignore parts from simulation 
761635 Create model for 1n6312US zener diode 
766239 Option to run PSpice on multi processors 
779909 Enhancement for PSpice to utilize Dual Processors 
807475 Enhancement for PSpice to utilize multi core Processors 
826041 IBIS v3.2 model support in PSpice 
842675 Default Maximum time step shows incorrect results 
860563 PSpice support on multicore processor 
862603 User would like a CD4015 model added to the AMS Simulator library 
871572 Enhancement: Add AutoConverge in probe window when convergence error occurs. 
877132 Enhancement request for HI302, HI303, HI549 parts 
878770 unix2dos should not be required on encrypted model 
879943 Need to enhance Model Editor translation support to IBIS 3.2 
881843 TCL : Enhancement: Suppress Warning for PSpice Netlist same as supported for Board 
flow 
892333 Ability to “save as” Capture-PSpice project directly along with all project related files. 
892479 IBIS to SPICE updated translator in Model Editor 
892494 Enhancement: Full encryption of spice model. 
894778 Description on the Libraries to be used in the Simulation and/or PCB Flow 
898282 Support of multi core Processors 
903823 IBIS to SPICE updated translator in Model Editor 
906185 An option to translate IBIS models version 2.0 in Model Editor 
916131 Enhancement : Upgrading dat file version to support higher precision 
918435 Question: Why default of 0.1%i used in Sensitivity Analysis? 
920707 Request for Zener Diode Model MMBZ4622-V 
921385 Multi-core processor support 
937741 PSpice support multicore 
952413 Request for Infineon IGBT Module FP25R12W2T4_B11 Model 
955644 Enhancement: Reduce memory footprint while reading multi-section data files. 
957800 IBIS v3.2 model support in PSpice 
958243 Model request for IGBT Modules 
968479 ENH:Update some PSpice templates 
982213 ERROR(ORPROBE-3191): Simulation message limit exceeded should be changed to 
Warning 
997908 Include documentation for VPWL_abm part in PSpice user guide 
1001268 Enhancement for PSpice to utilize multi core Processors 
1023336 ENH:Include basic fuse part in PSpice standard libraries 
1023641 Integrate resolver model with PSpice library set. 
1031587 ENH: Add tolerance to parameters for AA model in SPICE2G 
836207 RF-PCB Autoplace to show ratsnest while placing different RF groups 
836232 RF-PCB Ability to snap a group of RF elements to specific location on board 
759748 Use common port name in IC Package and PCB projects and export as PinName to SiP 
Layout and Allegro PCB. 
898161 Enhancement Add File Manager to SCM 
952817 Unable to generate document schematic 
958411 Prefer not seeing a page with just nets listed 
1012073 Schematic generation setting schematic grid units is very ambiguous. Change to typical 
grid settings or improve the help 
815480 font type/size changes for Text in sigxp canvas 
843705 SigXP: want to change the parameter of multiple elements with the same parameter at 
the same time 
844044 SigXP: Selecting/Highlighting element by clicking the text. 
891783 When we copy an element that is associated with a layer stack, the layer stack 
information is not copied. 
897926 Layer stack up information is not updated on the topology in the same session. 
751721 Via modeling enhancement 
831218 want a stop button in the Model Solution form of EMS2D 
862347 Want Cancel All button in Resolve Errors manually form. 
863574 Need Check All command in Setup Component Classes in SI Design Setup. 
863718 Abort button for stopping List Coupled Xnets. 
863737 Net name suffix and DiffPair name prefix for Diff Pairs Setup. 
863765 SI Design Setup: want to display and change the "Model Defined Diff Pairs" in the 
Setup Diff Pairs form 
866000 Want to translate s-param touchstone file to dml in SI Model Browser. 
868032 Enhancement: improved passivity check with S-parameters 
875009 Enhancement in Importing Cross Section from one board file to another. 
893462 Request - ability to create unique name for the device.dml and interconn.iml file 
944490 Would like to gray out Ignore Library for index files 
945829 Ability to import and export design audit results 
945945 Request - Audit screen to remain on the last item of a range selection 
954952 Enhancements to SI Audit Errors Report 
955456 Control possible power/ground net names 
955457 Would like to change the name of the "Dangling Lines" check in Design Audit 
955458 Would like to see RMB > More Info about Dielectric check in SI Design Audit 
961880 Enhancement to load the assignment map file for models during the SI Design Setup 
phase 
967947 Z-copy command in PCB SI 
976093 Request the variable MAX_MAPPINGS_FACTOR be added to the Setup -User 
Preferences form 
998274 Length calculate in System level 
1001887 Need IGNORE_MAPPING_DISCRETE_VALUES variable added to User Preferences 
form 
233320 Allow fixing multiple fields in die generator 
320770 Auto create die flag. 
415784 create spacer derived from a die given a shrink factor 
434012 Need to be able to specify cavity boundary and depth in SIP Die Stack Editor 
455674 Request cavity support for wirebond dies 
469477 Cannot place spacer and die on same die layer 
532990 ADRC check wire end to ring edge spacing 
533549 Wire to Substrate End to Soldermask Spacing Min Bond Finger Spacing should be 
applied on merged soldermask opening 
541095 Request for Cavity support in Die Stack Editor for new technology 
607813 Package cavity support enhancement 
615149 implement mold cap height for 3d viewer 
626679 16.2 Need component outline created for each DIE within DIE STACK on unique 
subclass 
648669 SiP Layout Die Generator - Need ability to lock Die Size, Pin Pitch and Edge Spacing 
and tool to auto generate # of pins 
653947 New rule in ADRC regarding tack points on bondfinger pads 
682279 Edit the already bonded power ground rings 
686138 Copy offset for clines 
730848 Stream out option to merge overlapping polygons on same layer during export 
766226 Provide a utility that will create a symbol for the cavity 
797118 Update component by Import Symbol Spreadsheet 
837298 Request to turn Auto Fill off when using the Die Generator to create DIE's. 
881037 Need component outline created for each DIE within DIE STACK on unique subclass 
882267 Enhancement request for cavity support in SIP 
882883 Add ability to place a pad/bondfinger using the wirebond non standard tool. 
901745 SiP degassing improvement request 
913996 Need to be able to create a Spacer with a cavity or opening. 
914244 Enhance database diary so that few selected entries can be deleted 
929214 stream out of bond wire without circles at the endpoints 
938442 Currently pin numbers are being used to generate the net name when auto create net is 
performed 
941013 PG ring edit command enhancement 
944376 3di file from 3d view should include board outline substrate outline for passing to 
solidworks 
945682 Increase the number of vertices use to depict the circle in stream out/GDSII output 
953243 Report on the total number of Bond Wires per quadrant. 
958437 sort macro names in library manager 
969227 Request the ability edit dimensioning text 
969276 Request the ability edit dimensioning text 
970667 Ability to edit dimension text with desired text including alphabets. 
978688 ENH: Ability to edit dimension text with desired text including alphabets & special 
characters. 
984589 Enhance the BGA generator command 
986587 Netname on plating bar should update on netlist import. 
986828 SiP layout need a method to replace single padstack with a via structure 
991325 Enhancement for the text to be included in the metal usage report if text is on conductor 
layer 
992698 user needs to put letters in dimension text and 16.5 dimension env doesn't allow it 
992742 allow user to paste in multiple values at a time in the process of creating new nets 
996754 Same pin name is shown in upper case and lower case in SCM after die text import 
1009986 request to put the assembly_top boundary of each die on different layers so that they can 
exported in films separately 
1012608 Rename padstack option in .sip Layout and updated Via List in CM with new padname 
1030897 Plating bar violations not highlighting the elements in violation. 
1030907 Enhance the Plating Bar Report tool to list the Errors first then the Warnings. 
995984 TDO needs CPM Entry to set default Shared Projects Location 
1012395 Need undo Checkout hierarchy option 
 
 
 
Bug CCRs: 
 
CCR ID Description 
140340 Gloss adds fillet, causing DRC for DIFFP_MIN_SPACE. 
277631 axlPolyOperation OR has incorrect results 
318520 Adding fillets is adding DRC to the design 
375572 via move causes thermal disconnect 
486545 Gloss adds Fillet on Diffpairs and creates shorts in PCB 
540578 Diff pairs do not slide together. 
620306 ODB++ export fails with oblong pads with 45 degree rotation 
687681 With NCdrill_Figure switched on, the holes of padless holes are not displayed. 
696853 Dyn_Fixed_therm_Width does not update 
840043 Split plane cannot void according to anti etch shape correctly. 
861680 Documentation needs to be changed for axlGetFindFilter 
862405 The "Assign Models to Complete" form is hidden behind PCB SI during SI Design Setup 
in some cases. 
867758 typo in documentation of axlCnsList 
900453 algroskill.pdf needs to include "name" as a DRC attribute 
905670 Allegro shadow mode status bar layer change 
917495 The property NODRC ETCH OUTSIDE KEEPIN is not working for cross hatched shape 
927931 Suspected typos in algroskill.pdf version 16.5 that should be corrected. 
930108 The “Value Returned” section is incorrectly documented for the skill function 
axlCursorWarp (). 
939242 Cross probing between Capture and Allegro is inconsistent 
942998 Skill - isInfinity() not working with prop dict entry range 
943410 axlDBCreatePropDictEntry() help is wrong 
947374 Shape will not obey the constraints and contract away from another shape. 
948164 ODB++ output error 
951080 When appmode = none CM select and show element does not work. 
952313 Allegro SKILL doc errors 
956581 Documentation error for axlShapeChangeDynamicType 
956599 axlCursorWarp documentation incorrect for RETURNS description. 
961068 Design Compare not working for OrCAD PCB Designer 
974288 Problem in converting 45 degree angled corners to Arc 
976066 BUG:Height added on place bound top as rectangle does not show in 3D 
981369 FSP pinswap results in FSP error expected file 100001.xml not created 
981658 Dynamic shape on TOP layer is not filling correcting and corrupting the shape. 
985939 Setting infinite value for cursor causes display problem 
988019 Allegro hangs when doing place replicate create 
989139 helpcmd and documentation still list color priority 
995934 wrong link for help button in "select library padstack" 
999672 Cline deleted from package symbol but it is not deleted on board after update symbol 
1001270 Dimension Move Text does not place it on the grid 
1001431 Shape check adds marker where visually it appears larger than the Minimum Aperture 
1002823 Need to remove obsolete command of Color Priority from the Documents 
1003382 Large database running DBdoctor taking over 24 hours 
1010824 Silkscreen adds elements that are closer than the specified element to pad clearance 
1013397 While copying the padstack after creation NC Legend show the filled NC Figure and not 
the padstack 
1014266 Rotation not working during Add Pin in package symbol 
1014271 Add circle displays default line width instead of one defined in Options tab. 
1014586 Moving a Via expands the pad display to the drill legend outline 
1016795 The "create device" default directory path should not follow the skillpath. 
1017173 moving a via changes its size to the NC figure 
1018826 Shape Filling problem 
1019507 Documentation for axlDesignFlip appears to be incorrect 
1020293 ODB++ Generation fail with Error gen_str-3 
1022137 Align Component Dialog Miss-identifies Units 
1024444 Update Symbols - Place Replicate Module does not update module 
1025976 allegro_viewer_plus visibility tab too small to display the ALL button win7-64 
1027582 Typo error in command window and log file 
1030890 High Speed USB Switch model 
1032904 Allegro crashing when using align component. 
1033695 Allegro crashing when using split plane. 
1034750 Shorts in Dynamic Shape 
1036569 Changes done in the Setup > Design Parameters > Design are not getting saved unless 
the brd is saved 
1038587 illegal character check in layer name 
1040576 axlPolyExpand doc is wrong 
1040631 axlSchedule.txt skill documentation file incorrect. contains the documentation for 
axlScheduleNet 
1041143 Shape on BOTTOM layer does not fill properly 
1043774 Remove net_short property when converting a static to a dynamic shape. 
1045609 Statement in the Viewlog for Update Symbol needs correction 
1047969 Some route path missed in .rou file. 
23849 compose shape takes extremely long time 
716906 Shapes are losing voids when editing traces. 
758792 wire bond add with Allow DRC violations set off shows unexpected behavior 
945472 Shape becomes unfilled after deleting via 
1051586 Stream out creates a bad file due to the top structure name 
13642 Problems with replace cache when parts are copied to new DSN 
27716 Corrupt library 
28078 connectivity incorrectly re-evaluated when port mirrored 
29178 Unexpected error in DB when open part in attached library 
30320 corrupt library, cannot delete part aliases cap0064 
35310 copying parts to a hierarchical page does not auto reference 
55359 two grid gap appears while placing wires 
114709 Wire is missing at the starting up to 1.5 grid (approx.) 
115833 Placing Sections of Heterogeneous parts need enhancement. 
158361 Capture Place wire looks unconnected 
206338 urgent - library, crash 
214376 Capture crashes opening a Library 
229606 Offpage connectors disappeared when GND symbol deleted. 
232731 Why capture places Heterogeneous parts wrongly? 
273524 Duplicate references in Capture 10.3 
337644 Edit while Place does not work for heterogeneous part 
372294 Ole storage error while opening design file 
373331 Title Block occurrence properties reset when TB is moved 
373714 Reference"SATA0" will become "SATA" 
380695 Ole storage error while opening design file 
388376 Ole storage error while opening design file 
389942 EXCEPTION_ACCESS_VIOLATION error while opening design file 
397503 Edit while Place does not work for heterogeneous part 
403843 EXCEPTION_ACCESS_VIOLATION error while opening any design file 
415982 EXCEPTION_ACCESS_VIOLATION error while opening design file 
435034 Auto reference placed parts does not work for hierarchical dsns 
464453 Getting DSM0020: Unable to Paste Object Error 
479199 Replace cache does not work on same library path 
502185 Offpage connectors disappeared when GND symbol deleted. 
509528 Replace Cache is not updating the timestamp resulting error DSM0020 : Unable to paste 
object. 
536039 Why capture places Heterogeneous parts wrongly? 
653792 ALG0078 while creating netlist 
673323 Star in tab system not functioning in same way for library and design 
767749 Graphic line property like color does not change after save 
774826 Why does Capture crash with the attached Design Files? 
787751 TCL: V16.3 should handle spaces of H-block reference during netlisting 
790111 Why capture gives "could not find .dsn" message when opening PSpice design for the 
second time? 
790414 P-CAD schematics get crash when converted to Capture. 
819020 Getting DSM0020: Unable to Paste Object Error 
849408 Designator doesn't gets assigned to heterogeneous part if designator is changed after 
selecting part 
852836 Ascend hierarchy option grayed out 
858454 Component gets locked if project closed with Part Editor open 
869528 Refdes increment on copying part is not with respect to occurrence value. 
873521 Could not find *.dsn warning when opening project 
879218 Copying a pin with help of CTRL key is giving error for overlapping pins 
887096 Editing excel doc(OLE object) after zooming into schematic affects size of spreadsheet 
on schematic 
889826 TCL: Diff Pairs not being created automatically even with _P & _N net syntax 
896315 heterogeneous part's section not updated on changing it 
896342 Intersheet Refs are coming in wrong side after rotating off-page connectors 
(OFFPAGELEFT_L) 
903000 Netlist Config File in Other Netlists is not working 
904366 Junction dots get added or deleted which changes in the net name when rotating the 
design 
930217 Net aliases does not get assigned to bus bits if bus name is checked in NETGROUP. 
931781 For Link “selected occurrence only” - DoNot Display Update Symbol Dialog 
935147 ORCAD Suppress Warning in Create Netlist>Setup issue while creating Netlist 
954858 Closed polyline used in pin shape is not appearing while using custom pin in part. 
964950 Modifying pin names using Split part command is not updating the part. 
992941 ERROR(ORCAP-19005) occurs when user tries to open second Capture application 
996435 Corrupt Library while doing save as 
1000127 Incremental annotation creates duplicate refdes 
1000506 Replace part in Design Cache not updating the values when same library is selected 
1000944 B1: Library corruption on renaming a part, editing and 'Save As' with a different name 
1001684 backannotation does not work if refdes is lowercase 
1003356 Version 4.7.3 of QtGui4.dll and QtCore.dll doesn’t allow Capture to invoke 
1008998 Net of a NETGROUP contains hierarchal block name and interrupting the connectivity 
1012459 E1: The error message "ERROR(ORCAP-19005)" is not descriptive 
1019298 Error (ORCAP-1558): Unexpected error in database access 
1024471 DRC does not report if both the pins of a 2 pin device are connected to same net. 
1029589 drawing diagonal wires in Fisheye view mode causes crash 
1033179 Finding Power\GNDs in Capture highlights other power and GND symbols. 
1044724 Suppress warning feature not working correctly. 
1045993 Capture crashes with the following steps. 
166156 Part Reference is truncated in  CIS BOM ,exported to EXCEL 
188124 Part Manager & BOM deletes the zero in the Ref Des 
232066 CIS BOM strips off the refdes from the - sign 
280531 CIS BOM removes the 0 from refdes X0 
297614 Refdes terminating abnormally in Part Manager and CIS BOM 
423363 Part Reference is truncated in  CIS BOM ,exported to EXCEL 
535051 refdes in CIS BOM got reset to C_ 
718954 CIS BOM and capture bom should show same results 
765647 Part manager does not accept the reference names having a mix of letters and numbers. 
841654 The RefDes get truncated while exporting CIS BoM to Excel. 
882384 Refdes is getting truncated in part manager if it is alphanumeric or contains hyphen in it. 
887219 Part information on page not updated to Part Manager's Group 
890277 Link or Update database part gives "Could not read part information XXX" message 
902677 Bezier curve in part graphics does not appear in CIS explorer window. 
925144 Same symbol generated different RefDes in BOM file which from Tools and Reports 
function 
932258 TCL:Verify Part Against (OLB) Libraries’ does not detect the path change of the part 
while verifying the part status. 
947275 Green sign indicate a variant part doesn't appear part manager in hierarchal design 
961838 Variant Status doesn't show a green check mark on linking part with multiple occurrence 
to database in complex hierarchy 
638221 Archiver should include templates.lib while archiving a PSpice project 
747613 Moving text with custom fonts suppresses custom font appearance 
760264 While moving text with custom fonts, fonts disappear and display in default fonts 
776933 Text font and size changes when we move it 
841741 Text font and size changes when we move it 
867632 Font changes from Arial to Concept Font when moving text 
887778 Text font changes to vector when moving text 
925568 Remove reference to non-CM enabled flow from the 16.5 Packager-XL Reference and 
DE HDL-CM User Guide 
960996 User cannot select the net in Global Navigation when tool tip is displaying. 
983074  character in attribute form causes Constraint manager  netrev to  crash 
1004084 Cannot save project 
1030121 How to use SUPPRESS_CONCAT_ERROR directive? 
1030728 net groups should not be allowed to be named with spaces or other illegal characters 
1041779 The font type of text will be changed during moving it 
1048049 Cadence Help - Hyperlinks does not work in Packager Setup-Layout page 
142976 pxl not generating pstcmbc.dat file if it finds control M 
843168 CM filter setting should not be inherited from the sub design when it is imported in top 
design 
878048 Interactive editing of differential pair is very slow. 
916423 CM color swatches working ok to Net objects not Diffpair and Bus object? 
944336 Tip of day appears when Setup –Constraints- Modes is selected through SCRIPT but not 
with the GUI 
950712 CM - Misspelling in form when changing class membership 
963826 Unable to set the MIN VIA GAP to default span checking from the Analysis Modes 
form. 
976556 Allegro Constraint Manager gives inconsistent analysis results 
979298 Constraint Manager should not allow to set Diff Pair Min Line Space bigger then neck 
gap 
1026738 $interfacepath value is blank, causing error if defined in local env file. 
934047 Variant Editor not showing customized columns 
1017051 Using space and parenthesis in sig_name causes issues in pxl and bom-hdl 
964889 Library > Edit Libraries menu option is missing after installing the latest hotfix 
996522 Set PATH for FSP when SPB is installed 
1008113 importing Altera constraints verilog to make virtual interface only small percentage of 
nets have IO standard 
1011470 Multi cell selection does not show the last cell selected 
1011949 Graphic issue and hence incorrect group highlights in xml editor(Rule Instance 
Editor/Edit Protocol) 
1024265 Few issues in FSP doc kit b001 
1024364 FSP diff engine issue 
1024652 Unable to import allegro board for attached 16.6 board when no lrf specified 
1027134 Qt warning message is displayed (Log) when you click twice on Termination Type 
column drop down box. 
1030322 power mapping editor form needs to be bigger by default and put the auto map regulators 
button on the left 
1030329 specify DE HDL symbol to generate GUI should NOT change the cell  name when the 
library is changed 
1032609 Import qsf into FSP fails with “PLL PLL_3 does not exist in device instance” 
907069 Bug:No Version in program links on Windows7 
971954 File Association in Switch release changes to hard path instead of CDSROOT for few 
tools 
945314 OrCAD Layout translation crashes Capture 
996019 PDV having text on 2 lines having CR/LF is lost when reloading the symbol 
1013775 Check-in block fails if only bus taps swapped in DEHDL 
1024509 starting Enable team design crashes after Design Studio message displays 
1024878 con2con metadataonly sets Version to UNRELEASED in revision.dat 
930093 Error:Fail to do the power network impedance analysis for given power/ground 
942727 PDN : Color map of Log and Linear does not change. 
968140 PDN happens crash while running DC-IRdrop 
1017080 PDN: Incorrect ESpice model assignment for 3 pin device. 
1029686 Preferences dialog can be launched multiple times from PDN form, 
1040770 PDN: F-element support. 
11695 Simulation seems to hang with large DAT output 
22614 Stimulus editor crashes with the sequence of steps 
105149 missing cd4046 part directory in Concept mix_misc library 
108504 Model Editor is not being registered by installer 
227655 Curly brackets {} expressions should be supported in AA flow 
555140 Wrong error Vj is negative reported by simulator - Vj cannot be negative 
606782 Need support for ITOL tolerance variable in AA_flow 
647097 Cut paste moves traces but not moved correctly. 
716792 TCL: Running AA MC with temperature sweep 
776553 Need support for ITOL tolerance variable in AA_flow 
874962 Temperature sweep generates Vj is negative 
878355 Unable to simulate with sub-circuit based part of a design which got created using Create 
Netlist > PSpice tab. 
893597 Material information disappears when you click next button under Data Entry > Core 
Details > Core. 
928393 Running AA MC with temperature sweep 
940954 Temperature sweep doesn’t work if VJ is negative 
973928 BUG:Current source has opposite direction 
996335 Bug: Encrypted lib not working for attached 
1023286 BUG: Edit profile in PSpice AA parametric plotter doesn’t reset to 1000 
1028606 Copy paste of trace having -sign turns trace into expression 
873178 Error in variable definition file 
969497 Unable to run any rfpcb command on this design 
1022902 Allegro to ADS translator crashes on libraries 
878802 Why does this part only allow for gate placement? 
886594 Lowercase for SCM TCL command? 
888598 CreferHDL Option form disappears behind Setup form - need to kill ASA 
933604 Signal connectivity lost when schematic block port name is changed 
956551 SCM 16.6 build 71 quits unexpectedly, when creating or opening a project, with or 
without Tdd_project env var set 
962707 SCM not updating the bga changed pin in a XML interface based PCB-Package co-
design 
973837 SCM: createInterface -createMode partially creates bus net members 
1006400 Incorrect warning in SCM due to way voltage value is stored in tabular and schematic 
blocks 
1006739 Not able to add the part using chips view in SCM this part works fine in DE HDL flow 
815123 actual width param of layer not imported into the layerstacks of sigxp LayerStack 
Manager 
822394 autosolve set to no is ignored if view trace parameters window is open 
834898 Cannot rotate selected elements by rotate icon if via was included. 
858828 Copying certain termination parts in SigXp results in display issue with parameter values 
922943 autosolve set to no is ignored if view trace parameters window is open 
1021356 Incorrect Error message for translating ibis of upper case file name. 
815920 tlsim sim result with s-param via was incorrect. 
868159 There is a difference of number of times of simulation between the signoise batch and 
GUI's Reports. 
917580 Bus Analysis data bit frequency using default value instead of strobe frequency 
937362 SI_MODEL_PATH variable is not correct in Allegro/SI when running from the Project 
Manager 
941876 Illegal model name cause pxl fail in 16.3 
947249 Probe List of Net browser opens in wrong directory 
947260 Signal Analysis window disappears when extracting a net 
967082 signoise command did not use Frequency set on Net. 
972909 Bus Sim: stimulus on diff data signals were not used correctly in comprehensive sim. 
987162 SI_MODEL_PATH of an environment variable is expanded at Add Directory command 
993706 Import logic is dropping ECSet relationship on certain model defined diff pairs 
998915 Dielectric value for a material is not taken from materials.dat file correctly 
999218 concept2cm has encountered a problem 
1019979 extracta batch command result is incorrect 
1033853 netrev crashes when importing logic 
894167 Cannot pour a Dynamic shape around existing signal traces on the bottom layer. 
921961 Incorrect error message SPMHLD-321 when OA_HOME is explicit set and die is not 
placed in CDNSIP 
956525 16.6 cdnsip crash when changing color's, use script and db to reproduce attached to this 
CCR 
956664 16.6 71 SiP Layout import of DIE through Standard DIE text in or Add Co-design DIE 
with wirebond chip down 
975803 Center of shape not filling with copper. 
1004948 envar icp_default_drawing_accuracy doesn't have any effect in 16.6 
1017982 Symbol Editor app mode -> Add Pin on DIE, crashes - The DIE was added using the SiP 
Wizard on new drawing