概要信息：

FEATURES

 LOW OFFSET VOLTAGE: 50µV max

 LOW DRIFT: 0.5µV/
C max

 LOW INPUT BIAS CURRENT: 5nA max

 HIGH CMR: 120dB min

 INPUTS PROTECTED TO 40V

 WIDE SUPPLY RANGE: 2.25V to 18V

 LOW QUIESCENT CURRENT: 700µA

 8-PIN PLASTIC DIP, SO-8
APPLICATIONS

 BRIDGE AMPLIFIER

 THERMOCOUPLE AMPLIFIER

 RTD SENSOR AMPLIFIER

 MEDICAL INSTRUMENTATION

 DATA ACQUISITION
DESCRIPTION
The INA128 and INA129 are low power, general
purpose instrumentation amplifiers offering excellent
accuracy. The versatile 3-op amp design and small size
make them ideal for a wide range of applications.
Current-feedback input circuitry provides wide
bandwidth even at high gain (200kHz at G = 100).
A single external resistor sets any gain from 1 to 10,000.
The INA128 provides an industry-standard gain
equation; the INA129 gain equation is compatible with
the AD620.
The INA128/INA129 is laser trimmed for very low offset
voltage (50µV), drift (0.5µV/°C) and high
common-mode rejection (120dB at G ≥ 100). It
operates with power supplies as low as ±2.25V, and
quiescent current is only 700µA—ideal for battery-
operated systems. Internal input protection can
withstand up to ±40V without damage.
The INA128/INA129 is available in 8-pin plastic DIP and
SO-8 surface-mount packages, specified for the –40°C
to +85°C temperature range. The INA128 is also
available in a dual configuration, the INA2128.
A1
A2
A3
40kΩ40kΩ
40kΩ40kΩ
VIN
2
1
8
3
6
5
VIN
RG
V+
V−
Ref
VO
G = 1 +
49.4kΩ
RG
−
+
4
7
NOTE: (1) INA129: 24.7kΩ
G = 1 +
50kΩ
RG
INA128, INA129
Over-Voltage
Protection
Over-Voltage
Protection
25kΩ(1)
25kΩ(1)
INA128:
INA129:
All trademarks are the property of their respective owners.
INA128
INA129
Precision, Low Power
INSTRUMENTATION AMPLIFIERS
SBOS051B − OCTOBER 1995 − REVISED FEBRUARY 2005

	  

 
    
   


  
    
    

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Copyright  1995−2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
	
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SBOS051B − OCTOBER 1995 − REVISED FEBRUARY 2005
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2
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage ±18V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 
Analog Input Voltage Range ±40V. . . . . . . . . . . . . . . . . . . . . . . . . . . 
Output Short-Circuit (to ground) Continuous. . . . . . . . . . . . . . . . . . 
Operating Temperature −40°C to +125°C. . . . . . . . . . . . . . . . . . . 
Storage Temperature Range −55°C to +125°C. . . . . . . . . . . . . . . . . 
Junction Temperature +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 
Lead Temperature  (soldering, 10s) +300°C. . . . . . . . . . . . . . . . . . . . . 
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by
ESD. Texas Instruments recommends that all
integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance
degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because very small parametric changes could cause the
device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this data
sheet.
PIN CONFIGURATION
RG
V−
IN
V+
IN
V−
RG
V+
VO
Ref
1
2
3
4
8
7
6
5
Top View
8-Pin DIP and SO-8
	
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3
ELECTRICAL CHARACTERISTICS  
At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
INA128P, U
INA129P. U
INA128PA, UA
INA129PA, UA
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
INPUT
Offset Voltage, RTI
Initial TA = +25°C ±10±100/G ±50±500/G ±25±100/G ±125±1000/G µV
vs Temperature TA =  TMIN to TMAX ±0.2±2/G ±0.5±20/G ±0.2±5/G ±1±20/G µV/°C
vs Power Supply VS = ±2.25V to ±18V ±0.2±20/G ±1±100/G ∗ ±2±200/G µV/V
Long-Term Stability ±0.1±3/G ∗ µV/mo
Impedance, Differential 1010 || 2 ∗ Ω || pF
Common-Mode 1011 || 9 ∗ Ω || pF
Common-Mode Voltage Range(1) VO = 0V (V+) − 2 (V+) − 1.4 ∗ ∗ V
(V−) + 2 (V−) + 1.7 ∗ ∗ V
Safe Input Voltage ±40 ∗ V
Common-Mode Rejection VCM = ±13V, ∆RS = 1kΩ
G = 1 80 86 73 ∗ dB
G = 10 100 106 93 ∗ dB
G = 100 120 125 110 ∗ dB
G = 1000 120 130 110 ∗ dB
BIAS CURRENT ±2 ±5 ∗ ±10 nA
vs Temperature ±30 ∗ pA/°C
Offset Current ±1 ±5 ∗ ±10 nA
vs Temperature ±30 ∗ pA/°C
NOISE VOLTAGE, RTI G = 1000, RS = 0Ω
f = 10Hz 10 ∗ nV/√Hz
f = 100Hz 8 ∗ nV/√Hz
f = 1kHz 8 ∗ nV/√Hz
fB = 0.1Hz to 10Hz 0.2 ∗ µVPP
Noise Current
f = 10Hz 0.9 ∗ pA/√Hz
f = 1kHz 0.3 ∗ pA/√Hz
fB = 0.1Hz to 10Hz 30 ∗ pAPP
GAIN
Gain Equation, INA128 1 + (50kΩ/RG) ∗ V/V
Gain Equation, INA129 1 + (49.4kΩ/RG) ∗ V/V
Range of Gain 1 10000 ∗ ∗ V/V
Gain Error G = 1 ±0.01 ±0.024 ∗ ±0.1 %
G = 10 ±0.02 ±0.4 ∗ ±0.5 %
G = 100 ±0.05 ±0.5 ∗ ±0.7 %
G = 1000 ±0.5 ±1 ∗ ±2 %
Gain vs Temperature(2) G = 1 ±1 ±10 ∗ ∗ ppm/°C
50kΩ (or 49.4kΩ) Resistance(2)(3) ±25 ±100 ∗ ∗ ppm/°C
Nonlinearity VO = ±13.6V, G = 1 ±0.0001 ±0.001 ∗ ±0.002 % of FSR
G = 10 ±0.0003 ±0.002 ∗ ±0.004 % of FSR
G = 100 ±0.0005 ±0.002 ∗ ±0.004 % of FSR
G = 1000 ±0.001 (4) ∗ ∗ % of FSR
NOTE: ∗ Specification is same as INA128P, U  or INA129P, U.
(1) Input common-mode range varies with output voltage — see typical curves.
(2) Specified by wafer test.
(3) Temperature coefficient of the 50kΩ (or 49.4kΩ) term in the gain equation.
(4) Nonlinearity measurements in G = 1000 are dominated by noise. Typical nonlinearity is ±0.001%.
	
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4
ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
INA128PA, UA
INA129PA, UA
INA128P, U
INA129P. U
PARAMETER UNITMAXTYPMINMAXTYPMINCONDITIONS
OUTPUT
Voltage: Positive RL = 10kΩ (V+) − 1.4 (V+) − 0.9 ∗ ∗ V
Voltage: Negative RL = 10kΩ (V−) + 1.4 (V−) + 0.8 ∗ ∗ V
Load Capacitance Stability 1000 ∗ pF
Short-Circuit Current +6/−15 ∗ mA
FREQUENCY RESPONSE
Bandwidth, −3dB G = 1 1.3 ∗ MHz
G = 10 700 ∗ kHz
G = 100 200 ∗ kHz
G = 1000 20 ∗ kHz
Slew Rate VO = ±10V, G = 10 4 ∗ V/µs
Settling Time, 0.01% G = 1 7 ∗ µs
G = 10 7 ∗ µs
G = 100 9 ∗ µs
G = 1000 80 ∗ µs
Overload Recovery 50% Overdrive 4 ∗ µs
POWER SUPPLY
Voltage Range ±2.25 ±15 ±18 ∗ ∗ ∗ V
Current, Total VIN = 0V ±700 ±750 ∗ ∗ µA
TEMPERATURE RANGE
Specification −40 +85 ∗ ∗ °C
Operating −40 +125 ∗ ∗ °C

JA 8-Pin DIP 80 ∗ °C/W
SO-8 SOIC 150 ∗ °C/W
NOTE: ∗ Specification is same as INA128P, U  or INA129P, U.
(1) Input common-mode range varies with output voltage — see typical curves.
(2) Specified by wafer test.
(3) Temperature coefficient of the 50kΩ (or 49.4kΩ) term in the gain equation.
(4) Nonlinearity measurements in G = 1000 are dominated by noise. Typical nonlinearity is ±0.001%.
	
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5
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±15V, unless otherwise noted.
−
GAIN vs FREQUENCY
60
50
40
30
20
10
0
10
20
G
ai
n
(d
B
)
Frequency (Hz)
1k 10k 100k 1M 10M
G = 100V/V
G = 10V/V
G = 1V/V
G = 1000V/V
−
POSITIVE POWER SUPPLY REJECTION
vs FREQUENCY
Frequency (Hz)
P
o
w
er
S
u
pp
ly
R
ej
ec
tio
n
(d
B
)
140
120
100
80
60
40
20
0
10 100 1k 10k 100k 1M
G = 100V/V
G = 1000V/V
G = 1V/V
G = 10V/V
INPUT COMMON−MODE RANGE
Output Voltage (V)
C
o
m
m
on
−
M
od
e
V
ol
ta
ge
(V
)
0 5 15
15
10
5
0
10
G = 1 G = 1
G ≥ 10 G ≥ 10
VD/2
+
+
VCM
VOVD/2 Ref
15V
+15V
+
−5−10−15
−
−
−
−5
−10
−15
vs OUTPUT VOLTAGE, VS = ±15V
COMMON−MODE REJECTION vs FREQUENCY
Frequency (Hz)
C
om
m
on
−
M
o
de
R
ej
e
ct
io
n
(d
B
)
10 100 10k 1M1k
140
120
100
80
60
40
20
0
100k
G = 1V/V
G = 10V/V
G = 100V/V
G = 1000V/V
NEGATIVE POWER SUPPLY REJECTION
vs FREQUENCY
Frequency (Hz)
P
ow
er
S
up
p
ly
R
ej
ec
tio
n
(d
B
)
140
120
100
80
60
40
20
0
10 100 1k 10k 100k 1M
G = 100V/V
G = 1000V/V
G = 1V/V
G = 10V/V
INPUT COMMON−MODE RANGE
Output Voltage (V)
C
o
m
m
on
−
M
od
e
V
ol
ta
ge
(V
)
5
4
3
2
1
0
0 1 2 3 4 5
G = 1 G = 1
G ≥ 10 G ≥ 10
G ≥ 10
G = 1
vs OUTPUT VOLTAGE, VS = ±5V, ±2.5V
−1
−2
−3
−4
−5
−1−2−3−4−5
VS = ±2.5V
VS = ±5V
	
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6
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15V, unless otherwise noted.
INPUT−REFERRED NOISE vs FREQUENCY
Frequency (Hz)
1 10 1k100
1k
100
10
1
10k
G = 1V/V
G = 10V/V
100
10
1
0.1
Current Noise
G = 100, 1000V/V
In
pu
t B
ia
s 
C
ur
re
nt
 N
oi
se
 (
pA
/√
H
z)
In
pu
t-
R
ef
er
re
d 
V
ol
ta
ge
 N
oi
se
 (
nV
/√
H
z )
QUIESCENT CURRENT and SLEW RATE
vs TEMPERATURE
0.85
0.8
0.75
0.7
0.65
0 6
6
5
4
3
2
1
0 25 50 75 100 125
IQ
Slew Rate
−75 −50 −25
Temperature (°C)
Q
ui
es
ce
nt
 C
ur
re
nt
 (
µA
)
S
le
w
 R
at
e 
(V
/µ
s)
INPUT OFFSET VOLTAGE WARM−UP
10
8
6
4
2
0
0 100 200 300 400 500
−2
−4
−6
−8
−10
Time (µs)
O
ffs
et
 V
ol
ta
ge
 C
ha
ng
e 
(µ
V
)
SETTLING TIME vs GAIN
Gain (V/V)
S
e
ttl
in
g
T
im
e
(m
s)
100
10
1
1 10 100 1000
0.01%
0.1%
INPUT OVER−VOLTAGE V/I CHARACTERISTICS
5
4
3
2
1
0
In
p
ut
C
ur
re
nt
(m
A
)
Input Voltage (V)
10 20 30 400 50
G = 1V/V
G = 1V/V
G = 1000V/V
G = 1000V/V VIN
IIN
+15V
Flat region represents
normal linear operation.
−1
−2
−3
−4
−5
−10−20−30−40−50
−15V
INPUT BIAS CURRENT vs TEMPERATURE
2
1
0
0 25 50 75 100 125
In
p
ut
B
ia
s
C
ur
re
nt
(n
A
)
IOS
IB
−25−50−75
−1
−2
Temperature (°C)
Typical IB and IOS
Range ±2nA at 25°C
	
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7
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15V, unless otherwise noted.
(V−)+1.2
(V−)
OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT
(V+)
0 1 2 3 4
Output Current (mA)
O
u
tp
ut
V
ol
ta
ge
(V
)
(V+)−0.4
(V+)−0.8
(V+)−1.2
(V−)+0.8
(V−)+0.4
(V−)+1.2
(V−)
(V+)
(V+)−0.4
(V+)−0.8
(V+)−1.2
(V−)+0.8
(V−)+0.4
OUTPUT VOLTAGE SWING
vs POWER SUPPLY VOLTAGE
0 5 10 15 20
Power Supply Voltage (V)
O
ut
pu
t
V
o
lta
ge
S
w
in
g
(V
)
RL = 10kΩ
−40°C
+85°C
+25°C
−40°C
+85°C
−40°C
+25°C
+85°C
SHORT−CIRCUIT OUTPUT CURRENT
vs TEMPERATURE
18
16
14
12
10
8
6
4
2
0
0 25 50 75 100 125
S
h
or
t−
C
ir
cu
it
C
u
rr
en
t
(m
A
)
−25−50−75
Temperature (°C)
−ISC
+ISC
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
Frequency (Hz)
P
e
ak
−
to
−
P
ea
k
O
ut
p
ut
V
ol
ta
ge
(V
P
P
)
30
25
20
15
10
5
0
1k 10k 100k 1M
G = 1
G = 10, 100
G = 1000
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
Frequency (Hz)
T
H
D
+
N
(%
)
100 1k 10k
1
0.1
0.01
0.001
100k
VO = 1Vrms G = 1
RL = 10kΩ
G = 10V/V
RL = 100kΩ
G = 100, RL = 100kΩ
G = 1, RL = 100kΩ
500kHz Measurement
Bandwidth
Dashed Portion
is noise limited.
	
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8
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15V, unless otherwise noted.
SMALL SIGNAL
(G = 1, 10)
G = 1
20mV/div
G = 10
5µs/div
SMALL SIGNAL
(G = 100, 1000)
G = 100
20mV/div
G = 1000
20µs/div
LARGE SIGNAL
(G = 1, 10)
G = 1
5V/div
G = 10
5µs/div
LARGE SIGNAL
(G = 100, 1000)
G = 100
5V/div
G = 1000
20µs/div
VOLTAGE NOISE 0.1 to 10Hz
INPUT−REFERRED, G ≥ 100
1s/div
0.1µV/div
	
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9
APPLICATIONS INFORMATION
Figure 1 shows the basic connections required for
operation of the INA128/INA129. Applications with noisy
or high impedance power supplies may require
decoupling capacitors close to the device pins as shown.
The output is referred to the output reference (Ref)
terminal which is normally grounded. This must be a
low-impedance connection to assure good
common-mode rejection. A resistance of 8Ω in series
with the Ref pin will cause a typical device to degrade
to approximately 80dB CMR (G = 1).
SETTING THE GAIN
Gain is set by connecting a single external resistor, RG,
connected between pins 1 and 8:
INA128:
G 
 1 50k

RG
INA129:
G 
 1 49.4k

RG
Commonly used gains and resistor values are shown in
Figure 1.
The 50kΩ term in Equation 1 (49.4kΩ in Equation 2)
comes from the sum of the two internal feedback
resistors of A1 and A2. These on-chip metal film
resistors are laser trimmed to accurate absolute values.
The accuracy and temperature coefficient of these
internal resistors are included in the gain accuracy and
drift specifications of the INA128/INA129.
The stability and temperature drift of the external gain
setting resistor, RG, also affects gain. RG’s contribution
to gain accuracy and drift can be directly inferred from
the gain equation (1). Low resistor values required for
high gain can make wiring resistance important.
Sockets add to the wiring resistance which will
contribute additional gain error (possibly an unstable
gain error) in gains of approximately 100 or greater.
DYNAMIC PERFORMANCE
The typical performance curve Gain vs Frequency
shows that, despite its low quiescent current, the
INA128/INA129 achieves wide bandwidth, even at high
gain. This is due to the current-feedback topology of the
input stage circuitry. Settling time also remains
excellent at high gain.
NOISE PERFORMANCE
The INA128/INA129 provides very low noise in most
applications. Low frequency noise is approximately
0.2µVPP measured from 0.1 to 10Hz (G ≥ 100). This
provides dramatically improved noise when compared
to state-of-the-art chopper-stabilized amplifiers.
RGAlso drawn in simplified form: INA128
Ref
VO
VIN
VIN
+
−
G 
 1
50k

RG
G 
 1
49.4k

RG
INA128: INA129:
DESIRED RG NEAREST RG NEAREST
GAIN (V/V) (Ω) 1% RG (Ω) (Ω) 1% RG (Ω

1 NC NC NC NC
2 50.00k 49.9k 49.4k 49.9k
5 12.50k 12.4k 12.35k 12.4k
10 5.556k 5.62k 5489 5.49k
20 2.632k 2.61k 2600 2.61k
50 1.02k 1.02k 1008 1k
100 505.1 511 499 499
200 251.3 249 248 249
500 100.2 100 99 100
1000 50.05 49.9 49.5 49.9
2000 25.01 24.9 24.7 24.9
5000 10.00 10 9.88 9.76
10000 5.001 4.99 4.94 4.87
INA128 INA129
NC: No Connection
A1
A2
A3
6
7
4
3
8
1
2
VIN
VIN
RG
V+
INA128, INA129
+
5
Over−Voltage
Protection
Over−Voltage
Protection
Load
+
VO
Ref
NOTE: (1) INA129: 24.7kΩ
−
0.1µF
0.1µF
−
V−
25kΩ(1)
25kΩ(1)
40kΩ 40kΩ
40kΩ 40kΩ
VO = G (VIN − VIN
+ −• )
Figure 1. Basic Connections
(1)
(2)
	
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10
OFFSET TRIMMING
The INA128/INA129 is laser trimmed for low offset voltage
and offset voltage drift. Most applications require no
external offset adjustment. Figure 2 shows an optional
circuit for trimming the output offset voltage. The voltage
applied to Ref terminal is summed with the output. The op
amp buffer provides low impedance at the Ref terminal to
preserve good common-mode rejection.
10kΩOPA177 100Ω
100Ω
1/2 REF200
1/2 REF200
V+
RG INA128
Ref
VO
VIN
VIN
+
−
 ±10mV
Adjustment Range
V−
100µA
100µA
Figure 2. Optional Trimming of Output Offset
Voltage
INPUT BIAS CURRENT RETURN PATH
The input impedance of the INA128/INA129 is
extremely high—approximately 1010Ω. However, a path
must be provided for the input bias current of both
inputs. This input bias current is approximately ±2nA.
High input impedance means that this input bias current
changes very little with varying input voltage.
Input circuitry must provide a path for this input bias
current for proper operation. Figure 3 shows various
provisions for an input bias current path. Without a bias
current path, the inputs will float to a potential which
exceeds the common-mode range, and the input
amplifiers will saturate.
If the differential source resistance is low, the bias
current return path can be connected to one input (see
the thermocouple example in Figure 3). With higher
source impedance, using two equal resistors provides
a balanced input with possible advantages of lower
input offset voltage due to bias current and better
high-frequency common-mode rejection.
47kΩ47kΩ
10kΩ
Microphone,
Hydrophone
etc.
Thermocouple
Center−tap provides
bias current return.
INA128
INA128
INA128
Figure 3. Providing an Input Common-Mode
Current Path
INPUT COMMON-MODE RANGE
The linear input voltage range of the input circuitry of the
INA128/INA129 is from approximately 1.4V below the
positive supply voltage to 1.7V above the negative
supply. As a differential input voltage causes the output
voltage increase, however, the linear input range will be
limited by the output voltage swing of amplifiers A1 and
A2. So the linear common-mode input range is related
to the output voltage of the complete amplifier. This
behavior also depends on supply voltage—see
performance curves, Input Common-Mode Range vs
Output Voltage.
Input-overload can produce an output voltage that
appears normal. For example, if an input overload
condition drives both input amplifiers to their positive
output swing limit, the difference voltage measured by
the output amplifier will be near zero. The output of A3
will be near 0V even though both inputs are overloaded.
LOW VOLTAGE OPERATION
The INA128/INA129 can be operated on power supplies
as low as ±2.25V. Performance remains excellent with
power supplies ranging from ±2.25V to ±18V. Most
parameters vary only slightly throughout this supply
voltage range—see typical performance curves.
	
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11
Operation at very low supply voltage requires careful
attention to assure that the input voltages remain within
their linear range. Voltage swing requirements of
internal nodes limit the input common-mode range with
low power supply voltage. Typical performance curves,
“Input Common-Mode Range vs Output Voltage” show
the range of linear operation for ±15V, ±5V, and ±2.5V
supplies.
300Ω
+5V
RG INA128 VO
Ref
2.5V − ∆V
2.5V + ∆V
Figure 4. Bridge Amplifier
INA128RG
VO
OPA130
Ref R1
1MΩ
=
1
2πR1C1
= 1.59Hz
VIN
+
f−3dB
C1
0.1µF
−
Figure 5. AC-Coupled Instrumentation Amplifier
REF102
R2R1
Pt100
Cu
Cu
V+
K
610.0V
4
2
INA128
VO
Ref
RG
R3
100Ω = Pt100 at 0°C
SEEBECK
ISA COEFFICIENT
TYPE MATERIAL (µV/
C) R1, R2
E + Chromel 58.5 66.5kΩ
− Constantan
J + Iron 50.2 76.8kΩ
− Constantan
K + Chromel 39.4 97.6kΩ
− Alumel
T + Copper 38.0 102kΩ
− Constantan
Figure 6. Thermocouple Amplifier with RTD
Cold-Junction Compensation
INA128RG
IB
R1
VIN
+
A1 IO
Load
Ref
IO 

VIN
R1
 G−
A1 IB ERROR
OPA177 ± 1.5nA
OPA131 ± 50pA
OPA602 ± 1pA
OPA128 ± 75fA
Figure 7. Differential Voltage to Current Converter
INA128RG/2
RG = 5.6kΩ
VOLA
RL
RA
10kΩ
Ref
G = 10
2.8kΩ
VG
VG
2.8kΩ
1/2
OPA2131
390kΩ
390kΩ
1/2
OPA2131 NOTE: Due to the INA128’s current-feedback
topology, VG is approximately 0.7V less than 
the common-mode input voltage. This DC offset 
in this guard potential is satisfactory for many
guarding applications.
Figure 8. ECG Amplifier with Right-Leg Drive
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
INA128P ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA128PA ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA128PAG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA128PG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA128U ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128UA ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128UAE4 ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128UAG4 ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA128UG4 ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129P ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA129PA ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA129PAG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA129PG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br)
CU NIPDAU N / A for Pkg Type
INA129U ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129UA ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jun-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
INA129UAE4 ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
INA129UG4 ACTIVE SOIC D 8 100 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
SN412014DRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
Cu NiPdAu Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jun-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
INA128U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA128UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA129U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA129UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Aug-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA128U/2K5 SOIC D 8 2500 346.0 346.0 29.0
INA128UA/2K5 SOIC D 8 2500 346.0 346.0 29.0
INA129U/2K5 SOIC D 8 2500 346.0 346.0 29.0
INA129UA/2K5 SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Aug-2008
Pack Materials-Page 2

MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 •  DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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